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Research questionHow can physical-aware logic synthesis improve PPA and closure time despite inaccurate wirelength estimates and large netlists?Traditional synthesis uses wirelength estimates that may poorly reflect later physical design, making power, performance, and area harder to optimize and prolonging closure. Large netlists also create memory and scalability constraints when physical structure is modeled.
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Latest papersRecent research connected to this question, newest first.LevelSyn: Physical-Aware Logic Synthesis via Level-Asynchronous Graph Neural NetworksThe source concerns And-Inverter Graph netlists and integration with the Berkeley ABC synthesis framework. It reports evidence on the EPFL benchmark suite and post-place-and-route design-rule validation; the abstract does not establish broader industrial deployment results.research paper · Sep 3, 2026
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